A semiconductor chip is typically a silicon die which incorporates a number of active/passive devices interconnected by a pattern of metal wires to form the desired circuit. In VLSI (Very Large Scale Integration) chips, these metal patterns are multilayered and each layer of metal wires is separated from one another by a layer of an insulating material. Interlevel contacts between two planes of metal wires are made by metal studs filling via-holes which are etched through said insulating layer. Cost reduction and circuit performance increase continue to place considerable demand on the manufacturing process to add supplementary wiring levels. However, the above described via-hole based technique, although widely used today, has multiple limitations and drawbacks as the number of wiring levels increases. With three or four levels of wiring levels being the current state of the art, it is absolutely mandatory to planarize the wafer surface at least after the first level of metallization (M1) has been completed. As a matter of fact, to reduce surface topography related problems associated with a non-planar surface, planarization has become a requirement. There are a number of planarization techniques, but chem-mech polishing (CMP) has demonstrated superior performance and results and as a consequence, it has become a widely accepted planarization technique for multilevel interconnects. CMP is a surface planarization method in which a wafer is rotated against a polishing pad in the presence of an abrasive and chemically reactive slurry while applying pressure. Among a number of advantages, CMP is perfectly adapted to produce planarized tungsten studs or lands according to the so-called dual damascene process of extensive use to date.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor structure 10 at five different stages of a classic dual-damascene process. In FIG. 1-1, a P type silicon substrate 11 has different field recess oxide (ROX) regions 12 that are used to isolate the devices formed in the substrate. In FIG. 1-1, only a single NFET 13 is shown for sake of simplicity. NFET 13 includes two diffused regions 14, typically the source and the drain regions, and a doped polysilicon gate electrode 15. Gate electrode 15 is isolated from substrate 11 by a thin dielectric layer 16. Typically, a layer of titanium di-silicide (TiSi.sub.2) is deposited on the diffused regions of the NFET 13 to reduce the contact resistance of the ohmic contacts to be subsequently formed therewith. A conductive doped polysilicon land 17 is formed atop a ROX region 12 as shown in the left hand part of FIG. 1-1. Spacers 18 are provided on the sidewalls of gate electrode 15 and polysilicon land 17 and total isolation thereof is achieved by an insulating cap (not shown). Insulating layers of Si.sub.3 N.sub.4 19 and borophosphosilicate glass (BPSG) 20 conformally coat the surface of structure 10.
The irregular surface of BPSG layer 20 is then planarized using a conventional CMP step adapted to polish the BPSG material. The structure 10 with a planar main surface 21 is shown in FIG. 1-2. Next, two different sized openings 22 and 23 are etched through Si.sub.3 N.sub.4 layer 19 and BPSG layer 20 to expose the top portion of polysilicon land 17 and polysilicon gate 15 respectively. Narrow opening 22, comprised of parts 22a and 22b, will be used as a via-hole for an electrical contact, while wide opening 23, comprised of parts 23a and 23b, is designed for receiving a conductive line or conductor. At this stage of the dual damascene process, the resulting structure is shown in FIG. 1-3. To that end, a two-step etch process is used, to ensure that each opening is comprised of these two parts. Then, as illustrated in FIG. 1-4, a titanium nitride (TiN) liner layer 24 and a tungsten layer 25 are conformally deposited in sequence onto the structure 10 top surface, for instance by low pressure chemical vapor deposition (LPCVD). As apparent from FIG. 1-4, the structure 10 surface is bumpy and therefore needs to be planarized again to remove the tungsten material in excess with respect to BPSG layer 20 main surface 21. This operation is also generally achieved by a CMP process. A detailed description of optimized operating conditions of a conventional CMP process for tungsten planarization will be given hereinbelow. The structure at the final stage of the dual damascene process, after tungsten planarization, is shown in FIG. 1-5. The remaining portions of tungsten layer 25 that fill openings 22 and 23 will be referred to as tungsten studs and will bear numerals 26 and 27 respectively. For consistency, stud 26 is comprised of parts 26a and 26b, while stud 27 is comprised of parts 27a and 27b as a result of the dual damascene process. Tungsten studs 26 and 27 form an electrical contact with the top surface of polysilicon land 17 and polysilicon gate 15 respectively. Tungsten studs 26 and 27 represent the M1 level of metallization. As apparent from FIG. 1-5, the width Wb of the upper part 27b of stud 27 is greater than the width Wa of the upper part 26b of stud 26 at the structure 10 surface. This is because part 27b will be used as a conductor as mentioned above, unlike part 26b which will be used as a contact. For convenience, upper parts 26b and 27b will be referred to hereinbelow as the narrow and wide tungsten lands. Unfortunately, at this ultimate stage of the dual damascene process, the surface of structure 10 is not as flat as it should be, but rather irregular as a result of the CMP process for tungsten planarization. As is clear from FIG. 1-5, the structure 10 surface exhibits a typical depression or cusp 28 so that the wide tungsten land 27b is not perfectly coplanar with the main surface 21 of the BPSG layer 20.
There are two causes to that cusp formation. First, the center region of the wafer is etched faster than the edge (or periphery) region and second, the wide tungsten lands (e.g. 27b) are etched faster than the narrow tungsten lands (e.g. 26b) irrespective of their location at the surface of the wafer. The problem is thus more acute for the wide tungsten lands situated at the center of the wafer. This erosion phenomena is referred to in the technical literature as the "dishing" effect. The cusp 28 (FIG. 1-5) produced during the conventional CMP process results from an undesired thinning of the thickness E of the wide tungsten land 27b. The dishing thus reflects an over-polishing of the wide tungsten lands which is detrimental to the sheet resistance thereof. As a matter of fact, the sheet resistance Rs linearly increases as the land thickness E decreases according to equation Rs=.rho./E wherein .rho. is the tungsten resistivity and may reach values outside the upper limit that is acceptable. The increase of the sheet resistance, in turn causes an increase of the land electrical resistance R which finally may lead to an unacceptable degradation of the overall device/circuit performance. However, over-polishing is necessary because under-polishing would even be a worse case with potential electrical shorts between adjacent wide tungsten lands. Therefore, the sheet resistance Rs of the wide tungsten lands and more particularly of those located at the center of the wafer, is an essential parameter of the specifications at this stage of the CMP process. If the sheet resistivity is too high, the wafer must be rejected. It is thus highly desired to have the sheet resistance of the wide tungsten lands maintained around the nominal value and it must be less than the acceptable limit given by the specifications to avoid wafer waste. As a consequence, from a production standpoint, the uniformity of the wide tungsten land sheet resistance around the nominal value, wafer to wafer in a same lot, and the reproducibility of this uniformity, lot to lot, are therefore important requirements.
Accordingly, much effort has been directed so far to modify the CMP processes and equipment in a continuous attempt to reduce the dishing effect and its negative impact on the wide tungsten land sheet resistance uniformity, in particular by optimizing the polishing rate. But, because the polishing time is determined by polishing a sample wafer, it significantly varies with a number of process parameters such as the tungsten deposition uniformity, so that the results of the CMP process vary from one wafer to another even in a same lot. As a result, in the case of tungsten planarization with a conventional CMP process, the tolerance (so-called the process window) on the polishing time is close to zero. The wafers are either under-polished (thus they require a new CMP pass to avoid the potential shorts between lands mentioned above) or over-polished which may cause a sheet resistance increase and in turn lead to the rejection of the wafer. The nominal sheet resistance value is very seldom attained on an uniform basis.
The experimental results given below illustrate the consequences of the dishing effect with a conventional CMP process. The wafers to be polished include the structure 10 of FIG. 1 wherein the BPSG layer 20 has a nominal thickness of 2000 nm and the tungsten layer 25 has a nominal thickness of 1600 nm (final thickness E remaining in land 27b: 1100 nm). The aim is to have a land 27b with a sheet resistance Rs of about 0.12 ohms/sq, the upper acceptable limit being of about 0.20 ohms/sq. The wafers were polished with a slurry consisting of alumina (Al.sub.2 O.sub.3) and ferric nitrate (Fe.sub.2 (NO.sub.3).sub.3) diluted in de-ionized (DI) water. The table/carrier speed ratio which is a key parameter of the CMP process was selected as 25/75 rpm as the best compromise for an optimized process. Nine lots of 25 wafers were processed according to the following operating conditions. The polishing time was determined using a sample wafer of the lot.
The conventional CMP process described below is in reality comprised of a preliminary step and a main step.
Preliminary step (slurry: Al.sub.2 O.sub.3 /Fe.sub.2 (NO.sub.3).sub.3 /DI water)
(1) Table/carrier speed: 25/75 rpm PA0 (2) Backside air: 1 psi PA0 (3) Arm oscillation: 10 mm PA0 (4) Oscillation speed: 10 mm/min PA0 (5) Slurry flow rate: 300 cc/min PA0 (6) Polish pressure: 2 psi PA0 (7) Pad temperature: 20.+-.5.degree. C. PA0 (8) Polishing time: 5 s PA0 (1) Table/carrier speed: 25/75 rpm PA0 (2) Backside air: 3 psi PA0 (3) Arm oscillation: 10 mm PA0 (4) Oscillation speed: 10 mm/min PA0 (5) Slurry flow rate: 100 cc/min PA0 (6) Polish pressure: 3.5 psi PA0 (7) Pad temperature: 20.+-.5.degree. C. PA0 (8) Polishing time: 600 s
Main step (slurry: Al.sub.2 O.sub.3 /F.sub.e 2(NO.sub.3).sub.3 /DI water)
FIG. 2 provides a physical representation of the thinning of a wide tungsten land 27b having a width Wb equal to 600 .mu.m caused by the dishing effect when measured with a profilometer for a wafer randomly selected among the nine lots. A profilometer allows an indirect measure of the dishing effect through a simple electrical resistance measurement. This measurement is based on equation R=.rho..multidot.L/S wherein .rho. is the tungsten resistivity, L and S are respectively the length and the section of the tungsten land 27b, because section S is a function of the land thickness E subject to thinning. Model DEKTAK sold by SLOAN TECHNOLOGY Corp., Santa Barbara, Calif., U.S.A. is adequate in all respects. As apparent from curve 29 in FIG. 2 which illustrates the depression 28 of FIG. 1-5, the thinning is not negligible in the center of the tungsten land 27b. In this particular case of this selected wafer, the height H of the depression is approximately equal to 350 nm. This value has to be compared with the thickness of 1100 nm of tungsten land 27b. More generally, from a number of experiments, it was observed that this height was varying between 350 and 550 nm.
In FIG. 3, curves 30 and 31 show the extreme variations of the average tungsten sheet resistance Rs of a few wide tungsten lands situated at different locations on the wafer (center/edge) for each wafer of these nine lots. The nominal value given by the specifications is equal to 0.12 ohms/sq. These sheet resistance variations between wafers of a same lot and between wafers of different lots are clearly not acceptable in the manufacture of advanced ICs. As apparent from FIG. 3, except for lots bearing numbers 7 and 9, all other runs have some wafers whose sheet resistance is above the upper limit given by the specifications which is 0.20 ohms/sq in this case. These wafers must be rejected which has a non-negligible cost.
In essence, although CMP is the most commonly polishing technique used today for planarizing semiconductor wafers at the final stage of the dual damascene process, the sheet resistance non uniformity of the wide tungsten lands at the center of the wafer, wafer to wafer and lot to lot (i.e. the reproducibility), remains a major concern.